The present invention relates to a non-volatile semiconductor memory device and, more particularly, to a non-volatile semiconductor memory device which has a self-aligned floating gate electrode formed by using a trench isolation structure and a method for producing the same.
FIGS. 16A to 18I show steps for producing a conventional non-volatile semiconductor memory device. As shown in FIG. 16A, linear trench isolations 2 are formed on a surface of a silicon semiconductor substrate by using a conventional technology. Then, the surface of the semiconductor substrate 1 is oxidized, thereby a tunnel film 3 made from silicon oxide is formed on the substrate 1. A polycrystalline silicon layer is deposited and a floating gate electrode 4 is formed from the polycrystalline layer using a lithography technology. The floating gate 4 extends linearly and parallel to the trench isolations 2. Then, n type ions are implanted into the substrate 1, thereby nxe2x88x92 diffusion layers 5 are formed parallel to the trench isolations 2.
Then, as shown in FIG. 16B, an insulating film made from silicon oxide is deposited over the top surface of the semiconductor substrate 1. The insulating film is then partially etched and remained on side walls of the floating gate electrodes 4 and, thereby, side spacers 6 are formed. Then, n+ diffusion layers 7 are formed parallel to the trench isolations 2 by an ion implantation technology.
Then, as shown in FIG. 16C, thick insulating layer 8xe2x80x2 having a thickness of about 5000-8000 xc3x85 is formed over the top surface of the semiconductor substrate 1.
Also, as shown in FIG. 17D, the thick insulating layer is polished so that the top of the floating gate electrode 4 is exposed by CMP method, thereby flat insulating layers 8 are formed.
Further, as shown in FIG. 17E, a polycrystalline silicon layer is deposited over the surface of the semiconductor substrate 1, and the polycrystalline silicon layer is etched to form fin-type floating gate electrodes 9. The fin-type floating gate electrodes 9 extend linearly and parallel to the floating gate electrodes 4.
Furthermore, as shown in FIG. 17F, an inter poly insulating film 10 is formed on the fin-type floating gate electrodes 9 and flat insulating layers 8. For example, the inter poly insulating film 10 is made from a multi-layer film (an ONO film) of silicon oxide, silicon nitride and silicon oxide films or a multi-layer film (an ONON film) of silicon oxide, silicon nitride, silicon oxide and silicon nitride films.
Then, a two-layer film 11 of conducting and insulating layers is deposited on the inter poly insulating film 10. Subsequently, as shown in FIG. 18G, illustrating a cross sectional view of a region with a word line, the two-layer film used for a control electrode 11 is remained. On the other hand, as shown in FIG. 18H, indicating a cross sectional view of a region without such a word line, the two-layer film is removed.
Further, as shown in FIG. 18I, the inter poly insulating films 10, the fin-type floating gate electrodes 9 and the floating gate electrodes 4 are removed in the region without the word line.
Then, a non-volatile semiconductor memory device shown in FIGS. 19A to 19C is completed. Note that FIG. 19A is a plan view of the non-volatile semiconductor memory device. Also, FIG. 19B is a cross sectional view of the region with a word line (along lines Axe2x80x94A), and FIG. 19C is a cross sectional view of the region without a word line (along lines Bxe2x80x94B).
The non-volatile semiconductor memory shown in FIGS. 19A to 19C comprises nxe2x88x92 diffusion layers 5 and n+ diffusion layers 7 extending parallel to the trench isolations 2, and forming source/drain regions of memory cells. Hereinafter, the source and drain regions are referred to as a source and the drain lines, respectively. These lines are called as bit lines of a memory device. While the control electrode 11 is formed perpendicular to the trench isolation 2, and the line is called as a word line of a memory device.
An equivalent circuit diagram of the non-volatile semiconductor memory is shown in FIG. 20. In the diagram, the circuit comprises n pieces of memory cell, and memory cells 1 to nxe2x88x921 are in write mode, and memory cell n is in erase mode. When reading information stored in the memory cell n, the drain line is biased to about 1V, the source line to 0V, the semiconductor substrate to 0V, the word lines 1 to nxe2x88x921 to 0V and the word line n to about 5 V as shown in FIG. 20.
However, the floating gate electrodes 4 may be formed out of the center of the two neighboring trench isolations 2, after these isolations 2 has been formed at the alignment step for the trench isolations 2. Therefore, the floating gate electrode 4 can often be shifted from the center of the isolations 2.
In FIG. 19B, when the floating gate electrode 4 is shifted from the center to the right, widths of the nxe2x88x92 diffusion layer 5 and n+ diffusion layer 7 formed at the right side of the floating gate electrode 4 are smaller than those of the nxe2x88x92 diffusion layer 5 and n+ diffusion layer 7 formed at the left side of the electrode 4. This results in that the resistance of the right drain line is higher than that of the left source line.
When the resistance of the drain line is higher than that of the source line, a voltage drop is occurred in the drain line. This presents the drain part of the memory cell n from being biased to 1V, although the drain line is biased to 1V. This in turn that the current flowing through the memory cell n becomes lower than Iread flowing in memory cell n at erase mode, therefore the memory cell n is erroneously detected to be in write mode.
Also, when misalignment of the floating gate electrode 4 against the center of the trench isolations 2 increases the resistance of the source or drain. Therefore, the length between the neighboring trench isolations 2 should be three times or more of the minimum resolution (F) using in lithography process. This results in that the unit memory cell 20 is 2 F long by 4 F wide and 8 F2 in area in minimum.
Further, as shown in FIG. 18I, an etching residue 12 in the shadow portion of the side spacer 6 after the removal of the floating gate electrode 4 in the portion where no word line is formed may connect electrically between the floating gate electrodes 4 of the neighboring memory cells.
Accordingly, the first object of the present invention is to provide a non-volatile semiconductor memory device which detects information in write/erase mode of the memory cell with a certain precision by forming a floating gate electrode at the center of the neighboring trench isolations.
Also, the second object of the present invention is to provide a highly integrated non-volatile semiconductor memory device which comprises a memory cell smaller than 8 F2 in area.
Also, the third object of the present invention is to provide a non-volatile semiconductor memory device which prevents a short-circuit between memory cells by removing etching residues on a side wall of a side spacer.
The present invention provides a method for producing a non-volatile semiconductor memory device. The method includes the steps of providing a semiconductor substrate having a surface, forming trench isolations on the substrate, the trench isolations being projected from the surface, forming source and drain regions between the neighboring trench isolations, so that the source and drain regions are faced each other across a channel region, and forming a floating gate electrode on the channel region through a tunnel film which is formed on the channel region.
By forming the floating gate electrode after forming the source/drain regions, the floating gate electrode can be formed at the center of the neighboring trench isolations, so that the width of the source region is substantially equal to that of the drain region and, thereby, resistance of the source region is substantially equal to that of the drain region. This prevents the malfunction of reading information from a memory cell.
Also, the present invention provides a method, wherein the step of forming source and drain regions comprising the steps of forming an oxide film comprising conductive impurities over the surface of the semiconductor substrate in which the trench isolations will be formed, etching the oxide film to form self-aligned side spacers on the side walls of the trench isolations, the side spacers being made from the oxide film remained on the side walls, and diffusing the impurities from the side spacers into the semiconductor substrate below the side spacers to form diffusion layers adjacent to the trench isolations, the diffusion layers becoming source and drain regions.
By forming the source/drain regions using the self-aligned side spacers, the floating gate electrode can be formed at the center of the neighboring trench isolations.
Also, the present invention provides a method, wherein the step of forming source and drain regions comprising the steps of forming a first oxide film comprising conductive impurities over the surface of the semiconductor substrate in which the trench isolations will be formed, etching the first oxide film to form self-aligned first side spacers on the side walls of the trench isolations, the first side spacers being made from the first oxide film remained on the side walls, forming a second oxide film comprising conductive impurities of which concentration is lower than that of the first oxide film over the top surface of the semiconductor substrate, etching the second oxide film to form self-aligned second side spacers on side walls of the first side spacers, the second side spacers being made from the second oxide film remained on the first side spacers, and diffusing the impurities from the first and second side spacers into the semiconductor substrate below the first and second side spacers to form high concentration diffusion layers adjacent to the trench isolations and low concentration diffusion layers adjacent to the first diffusion layers, the first and second diffusion layers becoming source and drain regions.
By forming the source/drain regions using the self-aligned side spacers, the floating gate electrode can be formed at the center of the neighboring trench isolations.
Also, by using the producing method, a memory cell having a LDD structure can be formed and, thereby, a memory cell having high reliability can be obtained.
Also, the present invention provides a method, wherein the step of forming source and drain regions comprising the steps of implanting impurities of first conduction type into the semiconductor substrate between the trench isolations to form a first conductive region, forming an oxide film over the semiconductor substrate, etching the oxide film to form self-aligned side spacers on the side walls of the trench isolations, the side spacers being made from the oxide film remained on the side walls, and implanting impurities of second conduction type into the semiconductor substrate using the side spacers for masks, so that the first conductive region in which the impurities of second conduction type are implanted becomes the channel region of second conductive type, while the first and second conductive regions facing to each other across the channel region become the source and drain regions.
By forming the source/drain regions using the self-aligned side spacers, the floating gate electrode can be formed at the center of the neighboring trench isolations.
Also, the present invention provides a method, wherein the step of forming source and drain regions comprising the steps of implanting impurities of first conduction type into the semiconductor substrate between the trench isolations to form a first conductive region, forming a first oxide film over the semiconductor substrate, etching the first oxide film to form self-aligned first side spacers on the side walls of the trench isolations, the first side spacers being made from the first oxide film remained on the side walls, implanting impurities of second conduction type into the semiconductor substrate using the first side spacers for masks, so that the first conductive region in which the impurities of second conduction type are implanted becomes a second conductive region, the second conductive region comprising impurities of first conductive type of which concentration is lower than that of the first conductive region, forming a second oxide film over the semiconductor substrate, etching the second oxide film to form self-aligned second side spacers on the side walls of the first side spacers, the second side spacers being made from the second oxide film remained on the side walls of the first side spacers, and implanting impurities of second conduction type into the semiconductor substrate using the second side spacers for masks, so that the second conductive region in which the impurities of second conduction type are implanted becomes the channel region of second conductive type, while the first and second conductive regions facing to each other across the channel region become the source and drain regions.
By using the producing method, the floating gate electrode can be made at the center of the neighboring trench isolations.
Also, by using the producing method, a memory cell having a LDD structure can be formed and, thereby, the memory cell of high stability can be obtained.
Preferably, the thickness of the oxide film is about xc2xc of the minimum resolution (F) of photolithography method for producing the non-volatile semiconductor memory device.
Thereby, a small-sized memory cell can be obtained.
Preferably, the thickness of the oxide film is about xc2xc of the gate length of the floating gate electrode.
Thereby, a small-sized memory cell can be obtained.
Also, the prevent invention provides a method, wherein the step of forming source and drain regions comprising the step of forming self-aligned side spacers on the side walls of the trench isolations, so that regions of the semiconductor substrate below the side spacers become the source and drain regions, and the step of forming the gate electrode comprising the step of forming the tunnel film and a polycrystalline silicon layer on the substrate across which the source and drain regions are facing to each other.
By using the method, the floating gate electrode can be formed at the center of the neighboring trench isolations.
The tunnel film may be a nitrided oxide film.
The polycrystalline silicon layer may be further formed on the side spacers.
By using such a structure, an area of a unit memory cell can be reduce without decreasing an area of the floating gate electrode which is facing to the control gate electrode.
Also, the prevent invention provides a method, wherein the step of forming the trench isolations comprises the steps of forming a multi-layer film comprising a lower oxide film and a silicon nitride film, the multi-layer film being thicker than the minimum resolution (F) of photolithography method for producing the non-volatile semiconductor memory device, forming a recess in the multi-layer film to expose the surface of the semiconductor substrate, embedding the recess by buried oxide film, and removing the multi-layer to project the buried oxide film above the surface of the semiconductor substrate, the buried oxide film becoming the trench isolation.
By using the method, the height of the trench isolation becomes more than the minimum resolution (F). Therefore, when the floating gate electrode is also formed on the side spacers, an area of a memory cell can be reduced, with maintaining an area 3 F2 or more of the floating gate electrode which is facing to the control gate electrode.
Also, the present invention provides a method, wherein the step of forming the trench isolations comprises the steps of forming a multi-layer film comprising a lower oxide film and silicon nitride film, the multi-layer film is thicker than gate length of the floating gate electrode, forming a recess in the multi-layer film to expose a surface of the semiconductor substrate, embedding the recess by buried oxide film, and removing the multi-layer to project the buried oxide film above the surface of the semiconductor substrate, the buried oxide film becoming the trench isolation.
By using the method, the height of the trench isolation becomes more than the gate length of the floating gate electrode. Therefore, when the floating gate electrode is also formed on the side spacers, an area 3 F2 or more of a memory cell can be reduced, with maintaining an area of the floating gate electrode which is facing to the control gate electrode.
The distance between the neighboring trench isolations may be about twice of the minimum resolution (F) of photolithography method for producing the non-volatile semiconductor memory device.
By using the method, the self-aligned floating gate electrode can be formed at the center of the neighboring trench isolations and, therefore, the distance between the neighboring trench isolations can be reduced. This results in that an area of a unit memory cell can be 6 F2.
The distance between the neighboring trench isolations may be about twice of the gate length of the floating gate electrode.
By using the method, the self-aligned floating gate electrode can be formed at the center of the neighboring trench isolations and, therefore, distance between the neighboring trench isolations can be reduced.
Also, the present invention provides a non-volatile semiconductor memory device. The memory device includes a semiconductor substrate having a surface, trench isolations formed substantially parallel to each other and projected from the surface, self-aligned side spacers formed on the side walls of the trench isolations, source and drain regions formed in the semiconductor substrate below the side spacers, a channel region formed in the semiconductor substrate between the source and drain regions, and a floating gate electrode formed on the channel region through a tunnel film.
According to the non-volatile semiconductor memory device, the floating gate electrode can be formed at the center of the neighboring trench isolations, so that the resistance of the source line is substantially equal to that of the drain line. This prevents the erroneously detection of the information of a memory cell.
Also, the self-aligned floating gate electrode can be formed at the center of the neighboring trench isolations and, thereby, the distance between the neighboring trench isolations can be reduced and an area of a unit memory cell can be also reduced.
Preferably, the source and drain regions are formed by diffusing impurities from the side spacers into the semiconductor substrate under the side spacers.
In this structure, the width of the source region is substantially equal to that of the drain region, and the floating gate electrode is formed at the center of the neighboring trench isolations.
Preferably, the source and drain regions are formed from the regions of the semiconductor substrate which are covered with the side spacers during the ion implantation process using the side spacers for masks.
In this structure, the width of the source region becomes substantially equal to that of the drain region, and the floating gate electrode is formed at the center of the neighboring trench isolations.
Each of the source and drain regions may comprise a first region adjacent to the trench isolation and a second region, the concentration of the impurities in the second region being lower than that of the first region.
In this structure, a memory cell has a LDD structure and, thereby a memory cell of high stability can be obtained.
Thickness of the tunnel film may be substantially constant.
This prevents the thinning of the tunnel film, so that the thickness of the tunnel film is substantially constant. Also, this prevents the concentration of the electric field at the thinned portion of the tunnel film.
The width of the side spacers are substantially equal to each other.
In this structure, the self-aligned spacers can be formed and, therefore, the width of the spacer is substantially equal to each other.
The width of the source region is substantially equal to that of the drain region.
In this structure, the self-aligned source and drain regions can be obtained and, thereby, the width of source and drain regions are substantially equal to each other.
Preferably, the distance between the neighboring trench isolations is about twice of the minimum resolution (F) of photolithography method for producing the non-volatile semiconductor memory device.
In this structure, the self-aligned source region or the like can be obtained and, a margin for the producing process can be reduced. Therefore, distance between the neighboring trench isolations can be reduced to about twice of the minimum resolution (F).
Preferably, the distance between the neighboring trench isolations is about twice of the gate length of the floating gate electrode.
In this structure, the self-aligned source region or the like can be obtained and, a margin for the producing process can be reduced. Therefore, the distance between the neighboring trench isolations can be reduced to about twice of the gate length of the floating gate electrode.
Preferably, the distance between the surface of the semiconductor substrate and a top of the trench isolation is substantially equal to the minimum resolution (F) of photolithography method for producing the non-volatile semiconductor memory device.
In this structure, an area of a unit memory cell can be reduced with maintaining an area of the floating gate electrode which is facing to the control gate electrode 3 F2 or more.
Preferably, the distance between the surface of the semiconductor substrate and a top of the trench isolation is substantially equal to the gate length of the floating gate electrode.
In this structure, an area of a unit memory cell can be reduced with maintaining an area of the floating gate electrode which is facing to the control gate electrode 3 F2 or more.
The floating gate is formed to cover a side wall of the trench isolation.
In this structure, an area of a unit memory cell can be reduced with maintaining an area of the floating gate electrode which is facing to the control gate electrode 3 F2 or more.
As can be seen from above description, by using the method for producing a non-volatile semiconductor memory device according to the present invention, the floating gate electrode can be formed in the center of the neighboring trench isolations. Thereby, a non-volatile semiconductor memory device of which source and drain lines have a certain resistance can be obtained.
Also, by using the method according to the present invention, an area of a memory cell becomes 6 F2, so that a highly integrated non-volatile semiconductor memory device can be obtained.
Also, by using the method according to the present invention, the short-circuit between neighboring memory cells caused by an etching residue can be prevented.